The difference between an instruction pointer and program counter

There is something very interesting about Tamarin, in that there is a distinction between the Instruction Pointer (IP) and Program Counter(PC) which as defined by wikipedia:

"The program counter, or shorter PC (also called the instruction pointer)"

Thus technically, they should be the same thing. So in Tamarin, the IP/PC are the same, but just for different interpreters. Let's take a closer look. What's weird is when an Interpreter state is created, we see:

wcodep ip;
InterpState state(f->pc,ip,sp,rp,f);

class InterpState
Frame* f;
Cursor pc;
wcodep ip;

With the following definitions for Cursor and wcodep:
typedef byte Token;
typedef const Token* wcodep;
typedef wcodep* wcodepp;
typedef const Token* Cursor;
So both are really just byte pointers. If both are just byte pointers, what is the difference between Cursor(pc) and wcodep(ip)? Let's take an in depth look at what IP is:

The initial value for IP in the inner(AKA FORTH) interpreter is:

inner(f, CODE_POS(w_interp), sp, rp);
void Interpreter::inner(Frame *f, wcodep ip, Box *sp, wcodepp rp);
Looking at CODE_POS:
#define CODE_POS(x) ((wcodep)code_pool + x##_offset)
Code pool refers to the Forth interpreter. Therefore, IP refers to the instruction pointer/program counter for the Forth interpreter. Now what about the PC?

The PC is initial set to 0 prior to being called in inner:

Frame *f = (Frame*)rstack;
memset(f, 0, sizeof(Frame));

inner(f, CODE_POS(w_interp), sp, rp);

Now the kicker is to look at the Forth word "NEXT":
PRIM(void, NEXT)(Interpreter& interp, Frame*& f, wcodep& ip, const Boxp sp)
// dispatch next ABC opcode
ip = code_pool+opcode_offsets[*f->pc++];
This is the magical glue between the two. The Frame->pc refers to the AVM2 bytecode program counter/ip, which means the current AVM2 opcode being executed. The Interpreter IP refers to the Forth Interpreter, thus the Forth word currently being executed.